Phase lock loops (PLL) are found in a myriad of electronic applications, such as communication receivers and clock synchronization circuits in computer systems, for providing a reference signal with a known phase for clocking incoming and out-going data. A conventional PLL comprises a phase detector for monitoring the phase difference between an input clock signal and the output signal of a voltage controlled oscillator (VCO) and generating an UP control signal and a DOWN control signal for a charge pump circuit which charges and discharges a loop filter at the input of the VCO. The UP and DOWN control signals drive the VCO to maintain a predetermined phase relationship between signals applied to the phase detector, as is well understood.
The output signal of the PLL must maintain a predetermined frequency of operation to be useful as a reference for clocking the incoming and out-going data. If the frequency of the input clock signal should drift, or even change to a radically different rate, the output signal of the VCO follows along and attempts to re-achieve phase lock thereto. Such behavior is inherent in the operation of the PLL. Many prior art systems have ways of detecting and reporting a momentary loss of phase lock. Yet, most if not all conventional phase lock indicators cannot distinguish the input frequency. Therefore, the output signal of the VCO locks to the new, albeit incorrect, frequency of the input clock signal and the lock indicator again reports a valid phase lock status. The reference signal thus clocks the incoming and out-going data at the wrong points resulting in erroneous communication.
The input clock signal may also become stuck-at-one or stuck-at-zero causing the PLL to permanently lose phase lock. Since the PLL cannot lock to a DC signal, the lock indicator suspends the system operation. While it is informative to know of the permanent loss of phase lock, the phase lock indicator does nothing toward restoring operation of the system which may remain down until the input clock signal is repaired. In many applications, it is desirable and even imperative that the PLL remain operational even if the primary input clock signal becomes invalid as a reference.
Hence, what is needed is an improved phase lock loop which re-establishes operation should the primary input clock signal become invalid.